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Integrated Circuit Systems, Inc.
ICS9179-12
3 DIMM Buffer
General Description
The ICS9179-12 is a buffer intended for reduced pin count 2 - chip Intel BX chipset designs An I2C interface is included, enabling individual outputs to be turned on or off. With 13 outputs, up to 3 DIMMs are supported.
Features

Thirteen high speed, low noise buffers, supports up to three SDRAM DIMMs. Buffer outputs skew matched to within 250 ps. I2C Serial Configuration interface to allow individual OUTPUTs to be stopped low. Multiple VDD, VSS pins for noise reduction 3.3V5% supply voltage 28-pin SOIC and SSOP package Propagation delay between 1 to 5.5ns Operation to 133MHz at 3.3V5%
Block Diagram Pin Configuration
28-Pin SOIC and SSOP
* Internal pull-up resistor of 100K Ohms to 3.3V on indicated inputs
Power Groups
VDD (0:4), GND (0:4) = Power supply for OUTPUT buffer VDDI, GNDI = Power supply for I2C circuitry
PentiumPro is a trademark of Intel Corporation I2C is a trademark of Philips Corporation 9179-12 Rev C 7/16/99
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
ICS9179-12
Pin Descriptions
PIN NUMBER 2, 3, 6, 7, 10, 11, 12, 18, 19, 22, 23, 26, 27 9 14 15 1, 5, 20, 24, 28 4, 8, 17, 21, 25 13 16 P I N NA M E OUTPUT (0:12) BU F _ I N SDATA SCLK VDD (0:4) GND (0:4) VDDI GNDI TYPE OUT IN I/O I/O PWR PWR PWR PWR DESCRIPTION Clock outputs1 Input for buffers D a t a p i n f o r I 2C c i r c u i t r y 3 C l o c k p i n f o r I 2C c i r c u i t r y 3 3.3V Power supply for OUTPUT buffers Ground for OUTPUT buffers 3.3V Power supply for I2C circuitry and internal logic G r o u n d f o r I 2C c i r c u i t r y a n d i n t e r n a l l o g i c
Notes: 1. At power up all thirteen OUTPUTs are enabled and active. 2. OE has a 100K Ohm internal pull-up resistor to keep all outputs active. 3. The SDATA and SCLK inputs both have internal pull-up resistors with values above 100K Ohms.
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ICS9179-12
Technical Pin Function Descriptions
VDD This is the power supply to the internal core logic of the device as well as the clock output buffers for OUTPUT (0:12). This pin operates at 3.3V volts. Clocks from the listed buffers that it supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels for the Clocks, please consult the DC parameter table in this data sheet. GND This is the power supply ground (common or negative) return pin for the internal core logic and all the output buffers. OUTPUT (0:12) These Output Clocks are use to drive Dynamic RAMs and are low skew copies of the CPU Clocks. The voltage swing of the OUTPUTs output is controlled by the supply voltage that is applied to VDD of the device, operates at 3.3 volts. I2C The SDATA and SCLOCK Inputs are used to program the device. The clock generator is a slave-receiver device in the I2C protocol. It will allow read-back of the registers. See configuration map for register functions. The I 2 C specification in Philips I2C Peripherals Data Handbook (1996) should be followed. BUF_IN Input for Fanout buffers (OUTPUT 0:12). VDDI This is the power supply to I2C circuitry.
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ICS9179-12
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit ICS (Slave/Receiver)
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit

How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS9179-12
Serial Configuration Command Bitmaps
Byte 0: OUTPUT Clock Register (Default=0) Byte 1: OUTPUT Clock Register
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# PWD 27 1 26 1 23 1 22 1 1 1 19 1 18 1 DESCRIPTION OUTPUT11 (Act/Inact) OUTPUT10 (Act/Inact) OUTPUT9 (Act/Inact) OUTPUT8 (Act/Inact) R e s e r ve d R e s e r ve d OUTPUT7 (Act/Inact) OUTPUT6 (Act/Inact)
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# 11 10 7 6 3 2
PWD 1 1 1 1 1 1 1 1
DESCRIPTION OUTPUT5 OUTPUT4 R e s e r ve d R e s e r ve d OUTPUT3 OUTPUT2 OUTPUT1 OUTPUT0
Byte 2: OUTPUT Clock Register
Functionality OE# 0 1 OUTPUT (0:13) Hi-Z 1 X BUF_IN
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD 1 12 1 1 1 1 1 1 1
DESCRIPTION R e s e r ve d OUTPUT12 (Act/Inact) R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
Notes: 1 = Enabled; 0 = Disabled, outputs held low Note: PWD = Power-Up Default
ICS9279-12 Power Consumption
The values below are estimates of target specifications.
Max 3.3V supply consumption Max discrete cap loads VDD = 3.465V All static inputs = VDD or GND 3mA 230mA 360mA 500mA
Condition No Clock Mode (BUF_IN - VDD1 or GND) I2C Circuitry Active Active 66MHz (BUF_IN = 66.66MHz) Active 100MHz (BUF_IN = 100.00MHz) Active 133MHz (BUF_IN = 133.33MHz)
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ICS9179-12
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input & Supply
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current SYMBOL VIH VIL IIH IIL IIL IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 Fi 1 CIN1 CONDITIONS MIN 2 VSS-0.3 -5 -60 80 120 160 180 240 300 10 TYP MAX UNITS VDD+0.3 V 0.8 V 5 uA uA uA 120 mA 180 mA 250 mA 230 mA 360 mA 500 mA 133 5 MHz pF
Operating Supply Current
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with 100K pull-up resistors CL = 0 pF; FIN @ 66MHz CL = 0 pF; FIN @ 100MHz CL = 0 pF; FIN @ 133MHz CL = 30 pF; RS=33; FIN @ 66MHz CL = 30 pF; RS=33; FIN @ 100MHz CL = 30 pF; RS=33; FIN @ 133MHz VDD = 3.3 V; All Outputs Loaded Logic Inputs
Input frequency Input Capacitance
1
Guarenteed by design, not 100% tested in production.
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ICS9179-12
Electrical Characteristics - Outputs
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time Skew1
1 1
SYMBOL RDSP RDSN VOH VOL IOH IOL Tr Tf Dt Tsk TPROP1 TPROP2 TPROPEN TPROPDIS
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -30 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 50% BIN to 10% OUT VT = 1.5 V VT = 1.5 V
MIN 10 10 2.6
TYP
40
MAX UNITS 24 24 V 0.4 V -54 mA mA 1.33 1.33 ns ns % ps ns ns ns ns
Duty Cycle
45 1 1 1 1
55 250 5.5 5 8 8
Propagation1
1
Guarenteed by design, not 100% tested in production.
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ICS9179-12
SYMBOL A A1 A2 b c D E e H L N 0.301 0.025 0 MIN. 0.068 0.002 0.066 0.010 0.004 0.205
COMMON DIMENSIONS NOM. 0.073 0.005 0.068 0.012 0.006 See Variations 0.209 0.0256 BSC 0.307 0.030 See Variations 4 MAX. 0.078 0.008 0.070 0.015 0.008 0.212
VARIATIONS N 14 16 20 24 28 30 MIN. 0.239 0.239 0.278 0.318 0.397 0.397
D NOM. 0.244 0.244 0.284 0.323 0.402 0.402 MAX. 0.249 0.249 0.289 0.328 0.407 0.407
0.311 0.037 8
28 Pin SSOP Package
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PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
ICS9179-12
LEAD COUNT DIMENSIONL
28L 0.704
SOIC Package Ordering Information
ICS9179M-12
Example:
ICS XXXX M - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type M=SOIC F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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